The power consumed by integrated circuits can be a critical factor in their utility in certain applications. For example, the power consumed by memory devices used in portable personal computers greatly affects the length of time they can be used without the need to recharge batteries powering such computers. Power consumption can also be important even where memory devices are not powered by batteries because it may be necessary to limit the heat generated by the memory devices.
In general, memory device power consumption increases with both the capacity and the operating speed of the memory devices. As the capacity of memory devices increase, for example, the memory devices contain more memory cells that must be periodically refreshed, and the number of address bits that must be received and processed increases. As the speed of memory devices increases, the large number of signal lines in the memory devices change state more rapidly, consuming power with each state change. Various approaches have been used to reduce the power consumption of memory devices. For example, techniques have been developed to reduce the required refresh rate of memory devices, to reduce the magnitude of the voltage needed to operate all or portions of memory devices, and to reduce the power consumed by memory devices when another memory device is being accessed. For example, power consumption has been reduced during certain DRAM refresh modes by removing power to input buffers when the DRAM is operating in such modes.
As is well known in the art, memory devices are generally coupled to controlling devices, such as memory controllers or system controllers, in a bus architecture. In a bus architecture, several memory devices are connected in parallel to each other and to the controlling device. As a result, when the controlling device is applying addresses or data to one memory device, all of the other memory devices also receive the addresses or data. The addresses and data are conventionally coupled to the data and addresses buses through receivers or input buffers, which may simply be inverters. Each time a data bit or address bit coupled to one of these receivers changes state, the receivers switch, thereby consuming power. Yet only one of the memory devices will use these data or addresses. The power consumed by switching the receivers in all of the other memory device thus constitutes wasted power.
One technique that has been used to reduce the power consumed by inactive memory devices is to remove power from data buffers in the inactive memory devices. Using this approach, each memory device decodes commands to determine when a command is being issued to access a memory device. Each memory device also decodes addresses to detect when a memory access is directed at that particular memory device. Control circuits in the memory device remove power to all of the data input buffers (also known as write receivers) until a write access is detected that is directed to that particular memory device. Similarly, the control circuits remove power to all of the data output buffers (also known as read transmitters) until a read access is detected that is directed to that particular memory device. By removing power to the write receivers and read transmitters unless a write access or read access, respectively, is directed to the memory device, a significant reduction in the power consumed by the memory device may be achieved.
Although power can be removed from the data receivers and transmitters when a memory device is inactive, power cannot similarly be removed from command and address receivers because they must be active to detect when a read or a write access is directed to that memory device. If power were removed from the command and address buffers, they would be unable to couple the command and address signals to internal circuitry that detects a read or a write access directed to that memory device.
Although selectively removing power to write receivers and read transmitters provides the benefit of reduced power consumption, this benefit comes at the price of reduced data access speed. More specifically, power does not begin to be applied to the write receivers in a conventional memory device until the memory device has decoded a write command and an address directed to that memory device. Until power has been fully applied to the write receivers, the write receivers cannot couple write data to circuitry in the memory device. In conventional memory devices it typically can require 6-8 ns to fully power-up the write receivers in the memory devices. When operating with a 300 MHz clock signal, for example, it will require 2 clock cycles before the write receivers can couple write data to internal circuitry. As a result, the minimum write latency of such memory device is 2 clock cycles. Yet it is often desirable for the write latency to be less that 2 clock cycles. The write latency of a memory device is normally set using a variety of techniques. For some memory devices, there is either no write latency, or the write latency is fixed at a predetermined number of clock cycles, such as I clock cycle. With other memory devices, the write latency is set by the user programming a mode register. In still other memory devices, the write latency is set by selecting the read latency of the memory device. The write latency may be, for example, 1 or 2 clock cycles less than the read latency. In this example, a minimum write latency of 2 clock cycles would limit the read latency to 3 or 4 clock cycles. Latencies of this magnitude can greatly slow the operating speed of conventional memory devices.
Although selectively removing power to write receivers in a memory device adversely affects the write latency of the memory device, selectively removing power to read transmitters in the memory device does not adversely affect the read latency of the memory device. The primary reason for this difference is that read data cannot be coupled from the memory device until well after a read command and a read address have been coupled to the memory device since the read data must first be accessed from an array of memory cells and then coupled to data bus terminals of the memory device. In contrast, write data can be coupled to the data bus terminals of the memory device along with or shortly after a write command and a write address have been coupled to the memory device since the write data is subsequently coupled to the array of memory cells. Thus, the problem of increased latencies caused by selectively removing power to receivers or transmitters exists only for removing power to write receivers.
There is therefore a need for a circuit and method that allows a memory device to operate in a low-power mode yet not adversely affect write latency in situations where achieving a minimum write latency is more critical than achieving reduced power.